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MC33363B High Voltage Switching Regulator
The MC33363B is a monolithic high voltage switching regulator that is specifically designed to operate from a rectified 240 Vac line source. This integrated circuit features an on-chip 700 V/1.0 A SENSEFETt power switch, 500 V active off-line startup FET, duty cycle controlled oscillator, current limiting comparator with a programmable threshold and leading edge blanking, latching pulse width modulator for double pulse suppression, high gain error amplifier, and a trimmed internal bandgap reference. Protective features include cycle-by-cycle current limiting, input undervoltage lockout with hysteresis, overvoltage protection, and thermal shutdown. This device is available in a 16-lead dual-in-line and wide body surface mount packages.
Features
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16 1 SO-16WB DW SUFFIX CASE 751N MC33363BDW AWLYYWWG
* * * * * * * * * *
On-Chip 700 V, 1.0 A SENSEFET Power Switch Rectified 240 Vac Line Source Operation On-Chip 500 V Active Off-Line Startup FET Latching PWM for Double Pulse Suppression Cycle-By-Cycle Current Limiting Input Undervoltage Lockout with Hysteresis Over-V oltage Protection Trimmed Internal Bandgap Reference Internal Thermal Shutdown Pb-Free Packages are Available*
A WL YY WW G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
PIN CONNECTIONS
Startup Input 1 16 Power Switch Drain
VCC
AC Input Startup Input Regulator Output 8 6 RT CT Osc 7 PWM Latch S Q PWM R Ipk Thermal LEB Compensation 9 EA 10 Voltage Feedback Input Driver OVP Startup Reg UVLO VCC 3 Overvoltage Protection Input 11 16 Power Switch Drain DC Output 1
3 4 13 GND 5 12 11 10 9 (Top View) Overvoltage Protection Input Voltage Feedback Input Compensation
GND RT Mirror CT Regulator Output 6 7 8
ORDERING INFORMATION
Device MC33363BDW MC33363BDWG MC33363BDWR2 Package SO-16WB SO-16WB (Pb-Free) Shipping 47 Units/Rail 47 Units/Rail
SO-16WB 1000 Tape & Reel
MC33363BDWR2G SO-16WB 1000 Tape & Reel (Pb-Free) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
GND
4, 5, 12, 13
Figure 1. Simplified Application
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
November, 2005 - Rev. 6
Publication Order Number: MC33363B/D
MC33363B
MAXIMUM RATINGS (Note 1)
Rating Power Switch (Pin 16) Drain Voltage Drain Current Startup Input Voltage (Pin 1, Note 2) Power Supply Voltage (Pin 3) Input Voltage Range Voltage Feedback Input (Pin 10) Compensation (Pin 9) Overvoltage Protection Input (Pin 11) RT (Pin 6) CT (Pin 7) Thermal Characteristics P Suffix, Dual-In-Line Case 648E Thermal Resistance, Junction-to-Air Thermal Resistance, Junction-to-Case DW Suffix, Surface Mount Case 751G Thermal Resistance, Junction-to-Air Thermal Resistance, Junction-to-Case Operating Junction Temperature Storage Temperature Symbol VDS IDS Vin VCC VIR Value 700 1.0 500 40 -1.0 to Vreg Unit V A V V V
C/W RqJA RqJC RqJA RqJC TJ Tstg 80 15 95 15 -25 to +150 -55 to +150 C C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per MIL-STD-883, Method 3015. Machine Model Method 200 V. 2. Maximum power dissipation limits must be observed. Thigh = +125C 3. Tested junction temperature range for the MC33363B: Tlow = -25C
ELECTRICAL CHARACTERISTICS (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin 8 = 1.0 mF, for typical values TJ = 25C, for min/max values TJ is the operating junction temperature range that applies (Note 3), unless otherwise noted.)
Characteristic REGULATOR (Pin 8) Output Voltage (IO = 0 mA, TJ = 25C) Line Regulation (VCC = 20 V to 40 V) Load Regulation (IO = 0 mA to 10 mA) Total Output Variation over Line, Load, and Temperature OSCILLATOR (Pin 7) Frequency CT = 390 pF TJ = 25C (VCC = 20 V) TJ = Tlow to Thigh (VCC = 20 V to 40 V) CT = 2.0 nF TJ = 25C (VCC = 20 V) TJ = Tlow to Thigh (VCC = 20 V to 40 V) Frequency Change with Voltage (VCC = 20 V to 40 V) ERROR AMPLIFIER (Pins 9, 10) Voltage Feedback Input Threshold Line Regulation (VCC = 20 V to 40 V, TJ = 25C) Input Bias Current (VFB = 2.6 V, TJ = 0 - 125C) Open Loop Voltage Gain (TJ = 25C) Gain Bandwidth Product (f = 100 kHz, TJ = 25C) Output Voltage Swing High State (ISource = 100 mA, VFB < 2.0 V) Low State (ISink = 100 mA, VFB > 3.0 V) VFB Regline IIB AVOL GBW VOH VOL 2.52 - - 70 0.85 4.0 - 2.6 0.6 20 82 1.0 5.3 0.2 2.68 5.0 500 94 1.15 - 0.35 V mV nA dB MHz V fOSC 260 255 60 59 DfOSC/DV - 285 - 67.5 - 0.1 310 315 75 76 2.0 kHz kHz Vreg Regline Regload Vreg 5.5 - - 5.3 6.5 30 44 - 7.5 500 200 8.0 V mV mV V Symbol Min Typ Max Unit
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MC33363B
ELECTRICAL CHARACTERISTICS (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin 8 = 1.0 mF, for typical values TJ = 25C, for min/max values TJ is the operating junction temperature range that applies (Note 4), unless otherwise noted.)
Characteristic OVERVOLTAGE DETECTION (Pin 11) Input Threshold Voltage Input Bias Current (Vin = 2.6 V, TJ = -25 - 125C) PWM COMPARATOR (Pins 7, 9) Duty Cycle Maximum (VFB = 0 V) Minimum (VFB = 2.7 V) POWER SWITCH (Pin 16) Drain-Source On-State Resistance (ID = 200 mA) TJ = 25C TJ = Tlow to Thigh Drain-Source Off-State Leakage Current (VDS = 650 V) TJ = 25C TJ = Tlow to Thigh Rise Time Fall Time OVERCURRENT COMPARATOR (Pin 16) Current Limit Threshold (RT = 10 k) STARTUP CONTROL (Pin 1) Peak Startup Current (Vin = 50 V) (TJ = -25 - 100C) VCC = 0 V VCC = (Vth(on) - 0.2 V) Off-State Leakage Current (Vin = 50 V, VCC = 20 V) UNDERVOLTAGE LOCKOUT (Pin 3) Startup Threshold (VCC Increasing) Minimum Operating Voltage After Turn-On TOTAL DEVICE (Pin 3) Power Supply Current Startup (VCC = 10 V, Pin 1 Open) Operating THERMAL SHUTDOWN Shutdown (Junction Temperature Increasing) Hysteresis (Junction Temperature Decreasing) 4. Tested junction temperature range for the MC33363B: Tlow = -25C Tsd TH Thigh = +125C - - 135 30 - - C ICC - - 0.25 3.2 0.5 5.0 mA Vth(on) VCC(min) 11 7.5 15.2 9.5 18 11.5 V V Istart 2.0 2.0 ID(off) - 5.0 5.0 40 8.0 8.0 200 mA mA Ilim 0.5 0.72 0.9 A RDS(on) - - ID(off) - - tr tf - - 0.25 - 50 50 1.0 50 - - ns ns 15 - 17 39 mA W % DC(max) DC(min) 48 - 50 0 52 0 Vth IIB 2.47 - 2.6 100 2.73 500 V nA Symbol Min Typ Max Unit
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MC33363B
I PK, POWER SWITCH PEAK DRAIN CURRENT (A 1.0 M f OSC , OSCILLATOR FREQUENCY (Hz)
CT = 100 pF
500 k C = 200 pF T 200 k CT = 500 pF 100 k CT = 1.0 nF 50 k 20 k
CT = 2.0 nF
VCC = 20 V TA = 25C
1.0 0.8 0.6 0.4 0.3 0.2 0.15 0.1 7.0 Inductor supply voltage and inductance value are adjusted so that Ipk turn-off is achieved at 5.0 ms. 10 15 20 30 40
VCC = 20 V CT = 1.0 mF TA = 25C
CT = 5.0 nF CT = 10 nF
10 k 7.0
10
15
20
30
50
70
50
70
RT, TIMING RESISTOR (kW)
RT, TIMING RESISTOR (kW)
Figure 2. Oscillator Frequency versus Timing Resistor
Figure 3. Power Switch Peak Drain Current versus Timing Resistor
0.8 I chg /I dscg , OSCILLATOR CHARGE/DISCHARGE CURRENT (mA) 0.5 VCC = 20 V TA = 25C
Dmax, MAXIMUM OUTPUT DUTY CYCLE (%)
70
RD/RT Ratio Discharge Resistor Pin 7 to GND
VCC = 20 V CT = 2.0 nF TA = 25C
60
0.3 0.2 0.15 0.1 0.08 7.0 10 15 20 30 50 70
50
40
30 1.0
RC/RT Ratio Charge Resistor Pin 7 to Vreg 2.0 3.0 5.0 7.0 10 TIMING RESISTOR RATIO
RT, TIMING RESISTOR (kW)
Figure 4. Oscillator Charge/Discharge Current versus Timing Resistor
Figure 5. Maximum Output Duty Cycle versus Timing Resistor Ratio
, EXCESS PHASE (DEGREES)
80 Gain 60 Phase 40 20 0
VCC = 20 V VO = 1.0 to 4.0 V RL = 5.0 MW CL = 2.0 pF TA = 25C
Vsat , OUTPUT SATURATION VOLTAGE (V)
A VOL, OPEN LOOP VOLTAGE GAIN (dB)
100
0 30 60 90
0 Source Saturation (Load to Ground) Vref
-1.0
- 2.0
120 150 180 10 M
2.0 1.0
Sink Saturation (Load to Vref) GND
VCC = 20 V TA = 25C
-20 10
100
1.0 k
10 k
100 k
1.0 M
0
0
0.2
0.4
0.6
0.8
1.0
f, FREQUENCY (Hz)
IO, OUTPUT LOAD CURRENT (mA)
Figure 6. Error Amp Open Loop Gain and Phase versus Frequency
Figure 7. Error Amp Output Saturation Voltage versus Load Current
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MC33363B
VCC = 20 V AV = -1.0 CL = 10 pF TA = 25C 20 mV/DIV VCC = 20 V AV = -1.0 CL = 10 pF TA = 25C 0.5 V/DIV 1.0 ms/DIV
1.80 V
3.00 V
1.75 V
1.75 V
1.70 V
0.50 V
1.0 ms/DIV
Figure 8. Error Amplifier Small Signal Transient Response
Figure 9. Error Amplifier Large Signal Transient Response
V reg, REGULATOR VOLTAGE CHANGE (mV)
0 I pk , PEAK STARTUP CURRENT (mA) VCC = 20 V RT = 10 k CPin 8 = 1.0 mF TA = 25C
6 5 4 3 2 1 0
VPin 1 = 50 V TA = 25C
-20
-40
-60
-80
0
4.0
8.0
12
16
20
0
2.0
4.0
6.0
8.0
10
12
Ireg, REGULATOR SOURCE CURRENT (mA)
VCC, POWER SUPPLY VOLTAGE (V)
Figure 10. Regulator Output Voltage Change versus Source Current
Figure 11. Peak Startup Current versus Power Supply Voltage
R DS(on), DRAIN-SOURCE ON-RESISTANCE ( )
32
ID = 200 mA
COSS, DRAIN-SOURCE CAPACITANCE (pF)
160 VCC = 20 V TA = 25C
24
120
16
80
8.0 Pulse tested at 5.0 ms with < 1.0% duty cycle so that TJ is as close to TA as possible. 0 -50 -25 0 25 50 75 100 125 150
40 COSS measured at 1.0 MHz with 50 mVpp. 10 100 1000 VDS, DRAIN-SOURCE VOLTAGE (V)
0 1.0
TA, AMBIENT TEMPERATURE (C)
Figure 12. Power Switch Drain-Source On-Resistance versus Temperature
Figure 13. Power Switch Drain-Source Capacitance versus Voltage
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MC33363B
3.2 CT = 390 pF I CC, SUPPLY CURRENT (mA) 2.4 CT = 2.0 nF 100 R JA , THERMAL RESISTANCE JUNCTION-TO-AIR (C/W) L = 12.7 mm of 2.0 oz. copper. Refer to Figures 16 and 17.
1.6 RT = 10 k Pin 1 = Open Pin 4, 5, 10, 11, 12, 13 = GND TA = 25C 0 10 20 VCC, SUPPLY VOLTAGE (V) 30 40
10
0.8
0
1.0 0.01
0.1
1.0 t, TIME (s)
10
100
Figure 14. Supply Current versus Supply Voltage
Figure 15. DW and P Suffix Transient Thermal Resistance
R JA , THERMAL RESISTANCE JUNCTION-TO-AIR ( C/W)
R JA, THERMAL RESISTANCE JUNCTION-TO-AIR (C/W)
80 60 40 20 PD(max) for TA = 70C RqJA
L
80 70 60 50 RqJA 40 30 0 10 20
Printed circuit board heatsink example
2.0 1.6 1.2 0.8 0.4
L
2.0 oz Copper
L 3.0 mm Graphs represent symmetrical layout
L 3.0 mm Graphs represent symmetrical layout
30
40
0 50
0
0
10
20
30
L, LENGTH OF COPPER (mm)
L, LENGTH OF COPPER (mm)
Figure 16. DW Suffix (SOP-16L) Thermal Resistance and Maximum Power Dissipation versus P.C.B. Copper Length
Figure 17. P Suffix (DIP-16) Thermal Resistance and Maximum Power Dissipation versus P.C.B. Copper Length
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IIIII IIIII
2.0 oz Copper
90
PD(max) for TA = 50C
Printed circuit board heatsink example
2.4
4.0 3.0 2.0 1.0 0 50
40
P D , MAXIMUM POWER DISSIPATION (W)
PD, MAXIMUM POWER DISSIPATION (W)
100
2.8
100
5.0
IIIII IIIII
MC33363B
PIN FUNCTION DESCRIPTION
Pin 1 Function Startup Input Description This pin connects directly to the rectified ac line voltage source. Internally Pin 1 is tied to the drain of a high voltage startup MOSFET. During startup, the MOSFET supplies internal bias, and charges an external capacitor that connects from the VCC pin to ground. This pin has been omitted for increased spacing between the rectified ac line voltage on Pin 1 and the VCC potential on Pin 3. This is the positive supply voltage input. During startup, power is supplied to this input from Pin 1. When VCC reaches the UVLO upper threshold, the startup MOSFET turns off and power is supplied from an auxiliary transformer winding. These pins are the control circuit grounds. They are part of the IC lead frame and provide a thermal path from the die to the printed circuit board. Resistor RT connects from this pin to ground. The value selected will program the Current Limit Comparator threshold and affect the Oscillator frequency. Capacitor CT connects from this pin to ground. The value selected, in conjunction with resistor RT, programs the Oscillator frequency. This 6.5 V output is available for biasing external circuitry. It requires an external bypass capacitor of at least 1.0 mF for stability. This pin is the Error Amplifier output and is made available for loop compensation. It can be used as an input to directly control the PWM Comparator. This is the inverting input of the Error Amplifier. It has a 2.6 V threshold and normally connects through a resistor divider to the converter output, or to a voltage that represents the converter output. This input provides runaway output voltage protection due to an external component or connection failure in the control loop feedback signal path. It has a 2.6 V threshold and normally connects through a resistor divider to the converter output, or to a voltage that represents the converter output. These pins have been omitted for increased spacing between the high voltages present on the Power Switch Drain, and the ground potential on Pins 12 and 13. This pin is designed to directly drive the converter transformer and is capable of switching a maximum of 700 V and 1.0 A.
2 3
- VCC
4, 5, 12, 13 6 7 8 9 10 11
Ground RT CT Regulator Output Compensation Voltage Feedback Input Overvoltage Protection Input - Power Switch Drain
14, 15 16
Capacitor CT Compensation Oscillator Output PWM Comparator Output PWM Latch Q Output Power Switch Gate Drive Leading Edge Blanking Input (Power Switch Drain Current) Normal PWM Operating Range Output Overload
2.6 V 0.6 V
Current Limit Propagation Delay Current Limit Threshold
Figure 18. Timing Diagram of Normal Operation
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MC33363B
AC Input Startup Input Current Mirror Startup Control Band Gap Regulator 2.25 I UVLO 14.5 V/ 9.5 V OVP PWM Latch S Q PWM Comparator R Leading Edge Blanking 8.1 Current Limit Comparator Compensation 405 2.6 V 10 Voltage Feedback Input 9 Error Amplifier Driver 2.6 V 16 Power Switch Drain 1
Regulator Output 6.5 V 8 I 6 RT
VCC 3 Overvoltage Protection Input 11 DC Output
4I Oscillator 7
CT
Thermal Shutdown
270 m A GND 4, 5, 12, 13
Figure 19. Representative Block Diagram
15.2 V VCC 9.5 V
Drain Current
Figure 20. Timing Diagram of Short-Circuit Condition
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MC33363B
OPERATING DESCRIPTION Introduction The MC33363B represents a new higher level of integration by providing all the active high voltage power, control, and protection circuitry required for implementation of a flyback or forward converter on a single monolithic chip. This device is designed for direct operation from a rectified 240 Vac line source and requires a minimum number of external components to implement a complete converter. A description of each of the functional blocks is given below, and the representative block and timing diagrams are shown in Figures 19, 18 and 20. Oscillator and Current Mirror The oscillator frequency is controlled by the values selected for the timing components RT and CT. Resistor RT programs the oscillator charge/discharge current via the Current Mirror 4 I output, Figure 4. Capacitor CT is charged and discharged by an equal magnitude internal current source and sink. This generates a symmetrical 50 percent duty cycle waveform at Pin 7, with a peak and valley threshold of 2.6 V and 0.6 V respectively. During the discharge of CT, the oscillator generates an internal blanking pulse that holds the inverting input of the AND gate Driver high. This causes the Power Switch gate drive to be held in a low state, thus producing a well controlled amount of output deadtime. The amount of deadtime is relatively constant with respect to the oscillator frequency when operating below 1.0 MHz. The maximum Power Switch duty cycle at Pin 16 can be modified from the internal 50% limit by providing an additional charge or discharge current path to CT, Figure 21. In order to increase the maximum duty cycle, a discharge current resistor RD is connected from Pin 7 to ground. To decrease the maximum duty cycle, a charge current resistor RC is connected from Pin 7 to the Regulator Output. Figure 5 shows an obtainable range of maximum output duty cycle versus the ratio of either RC or RD with respect to RT.
Current Mirror 2.25 I I RC RT 4I CT 7 Oscillator Blanking Pulse 6 Current Limit Reference
The formula for the charge/discharge current along with the oscillator frequency are given below. The frequency formula is a first order approximation and is accurate for CT values greater than 500 pF. For smaller values of CT, refer to Figure 2. Note that resistor RT also programs the Current Limit Comparator threshold.
I 5.4 +R chg dscg T I f[ chg dscg 4C T
PWM Comparator and Latch The pulse width modulator consists of a comparator with the oscillator ramp voltage applied to the non-inverting input, while the error amplifier output is applied into the inverting input. The Oscillator applies a set pulse to the PWM Latch while CT is discharging, and upon reaching the valley voltage, Power Switch conduction is initiated. When CT charges to a voltage that exceeds the error amplifier output, the PWM Latch is reset, thus terminating Power Switch conduction for the duration of the oscillator ramp-up period. This PWM Comparator/Latch combination prevents multiple output pulses during a given oscillator clock cycle. The timing diagram shown in Figure 18 illustrates the Power Switch duty cycle behavior versus the Compensation voltage. Current Limit Comparator and Power Switch The MC33363B uses cycle-by-cycle current limiting as a means of protecting the output switch transistor from overstress. Each on-cycle is treated as a separate situation. Current limiting is implemented by monitoring the output switch current buildup during conduction, and upon sensing an overcurrent condition, immediately turning off the switch for the duration of the oscillator ramp-up period. The Power Switch is constructed as a SENSEFET allowing a virtually lossless method of monitoring the drain current. It consists of a total of 1462 cells, of which 36 are connected to a 8.1 W ground-referenced sense resistor. The Current Sense Comparator detects if the voltage across the sense resistor exceeds the reference level that is present at the inverting input. If exceeded, the comparator quickly resets the PWM Latch, thus protecting the Power Switch. The current limit reference level is generated by the 2.25 I output of the Current Mirror. This current causes a reference voltage to appear across the 405 W resistor. This voltage level, as well as the Oscillator charge/discharge current are both set by resistor RT. Therefore when selecting the values for RT and CT, RT must be chosen first to set the Power Switch peak drain current, while CT is chosen second to set the desired Oscillator frequency. A graph of the Power Switch peak drain current versus RT is shown in Figure 3 with the related formula below.
I pk + 8.8 T - 1.077 1000 R
Regulator Output 1.0 8
RD
PWM Comparator
Figure 21. Maximum Duty Cycle Modification
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MC33363B
The Power Switch is designed to directly drive the converter transformer and is capable of switching a maximum of 700 V and 1.0 A. Proper device voltage snubbing and heatsinking are required for reliable operation. A Leading Edge Blanking circuit was placed in the current sensing signal path. This circuit prevents a premature reset of the PWM Latch. The premature reset is generated each time the Power Switch is driven into conduction. It appears as a narrow voltage spike across the current sense resistor, and is due to the MOSFET gate to source capacitance, transformer interwinding capacitance, and output rectifier recovery time. The Leading Edge Blanking circuit has a dynamic behavior in that it masks the current signal until the Power Switch turn-on transition is completed. The current limit propagation delay time is typically 262 ns. This time is measured from when an overcurrent appears at the Power Switch drain, to the beginning of turn-off. Error Amplifier An fully compensated Error Amplifier with access to the inverting input and output is provided for primary side voltage sensing, Figure 19. It features a typical dc voltage gain of 82 dB, and a unity gain bandwidth of 1.0 MHz with 78 degrees of phase margin, Figure 6. The noninverting input is internally biased at 2.6 V 3.1% and is not pinned out. The Error Amplifier output is pinned out for external loop compensation and as a means for directly driving the PWM Comparator. The output was designed with a limited sink current capability of 270 mA, allowing it to be easily overridden with a pullup resistor. This is desirable in applications that require secondary side voltage sensing. Overvoltage Protection An Overvoltage Protection Comparator is included to eliminate the possibility of runaway output voltage. This condition can occur if the control loop feedback signal path is broken due to an external component or connection failure. The comparator is normally used to monitor the primary side VCC voltage. When the 2.6 V threshold is exceeded, it will immediately turn off the Power Switch, and protect the load from a severe overvoltage condition. This input can also be driven from external circuitry to inhibit converter operation. Undervoltage Lockout An Undervoltage Lockout comparator has been incorporated to guarantee that the integrated circuit has sufficient voltage to be fully functional before the output stage is enabled. The UVLO comparator monitors the VCC voltage at Pin 3 and when it exceeds 14.5 V, the reset signal is removed from the PWM Latch allowing operation of the Power Switch. To prevent erratic switching as the threshold is crossed, 5.0 V of hysteresis is provided. Startup Control An internal Startup Control circuit with a high voltage enhancement mode MOSFET is included within the MC33363B. This circuitry allows for increased converter efficiency by eliminating the external startup resistor, and its associated power dissipation, commonly used in most off-line converters that utilize a UC3842 type of controller. Rectified ac line voltage is applied to the Startup Input, Pin 1. This causes the MOSFET to enhance and supply internal bias as well as charge current to the VCC bypass capacitor that connects from Pin 3 to ground. When VCC reaches the UVLO upper threshold of 15.2 V, the IC commences operation and the startup MOSFET is turned off. Operating bias is now derived from the auxiliary transformer winding, and all of the device power is efficiently converted down from the rectified ac line. The startup MOSFET will provide a steady current of 1.7 mA, Figure 11, as VCC increases or shorted to ground. The startup MOSFET is rated at a maximum of 400 V with VCC shorted to ground, and 500 V when charging a VCC capacitor of 1000 mF or less. Output Short-Circuit Condition When the output is short-circuited, the VCC is powered by the internal startup circuit instead of the VCC auxiliary winding. The internal startup circuit turns on and charges up VCC voltage when VCC reaches its UVLO lower threshold of 9.5V. It turns off and VCC voltage drops when VCC reaches its UVLO upper threshold of 15.2V. The device only delivers drain current for the time when VCC goes from 15.2V to 9.5V. No drain current is delivered when VCC goes from 9.5V to 15.2V. As a result, some of the switching cycle is missed as shown in Figure 20. The drain current limit is limited by the cycle-by-cycle current limit. Regulator A low current 6.5 V regulated output is available for biasing the Error Amplifier and any additional control system circuitry. It is capable of up to 10 mA and has short-circuit protection. This output requires an external bypass capacitor of at least 1.0 mF for stability. Thermal Shutdown and Package Internal thermal circuitry is provided to protect the Power Switch in the event that the maximum junction temperature is exceeded. When activated, typically at 135C, the Latch is forced into a `reset' state, disabling the Power Switch. The Latch is allowed to `set' when the Power Switch temperature falls below 105C. This feature is provided to prevent catastrophic failures from accidental device overheating. It is not intended to be used as a substitute for proper heatsinking. The MC33363B is contained in a heatsinkable plastic dual-in-line package in which the die is mounted on a special heat tab copper alloy lead frame. This tab consists of the four center ground pins that are specifically designed to improve thermal conduction from the die to the circuit board. Figures 16 and 17 show a simple and effective method of utilizing the printed circuit board medium as a heat dissipater by soldering these pins to an adequate area of copper foil. This permits the use of standard layout and mounting practices while having the ability to halve the junction to air thermal resistance. The examples are for a symmetrical layout on a single-sided board with two ounce per square foot of copper.
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MC33363B
PACKAGE DIMENSIONS
SO-16WB DW SUFFIX CASE 751N-01 ISSUE O
-A- T
16 9
-B-
1 8
P
0.010 (0.25)
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R S T MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 2.54 BSC 3.81 BSC INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 0.100 BSC 0.150 BSC
J
13X
D
M
0.010 (0.25)
TA
S
B
S
F R X 45_ C -T-
S
9X
K G
SEATING PLANE
M
The product described herein (MC33363B), may be covered by one or more of the following U.S. patents: 4,553,084; 5,418,410; 5,477,175. There may be other patents pending. SENSEFET is a trademark of Semiconductor Components Industries, LLC (SCILLC)
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MC33363B/D

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